Guaranteeing correctness in parallel application execution requires hardware atomic synchronization instructions. Such instructions ensure that if multiple processor cores try to concurrently update the same variable, only one processor core will succeed. Some examples of atomic synchronization instructions supported by current hardware include load-link/store-conditional, compare-and-swap, fetch-and-increment, etc.
Synchronization instructions only return binary notifications of success (win) or failure (loss) to the processor cores, causing an information gap between the hardware and the software. Therefore, a processor core only receives a notification of whether its update was successful. However, arbiters or other resource synchronization and management components on an interconnection network between the processor cores and resources do not share other information related to a successful/failed update. Therefore, information is lost between atomicity hardware and the instruction set architecture.
Exclusive access to a resource by two or more processor cores that are executing concurrently may be obtained by executing atomic synchronization instructions in order to gain access to said resource. The processor core that executes the synchronization instruction successfully will have obtained exclusive access to the resource.
Exclusive access to a contended resource may also be granted to a processor core issuing a resource access request for the contended resource on a first come first serve basis. A resource manager can determine whether to grant or deny access to a resource access request issued by any of the processor cores, i.e., requester processor core, based on availability of the contended resource.